Test probe structure

ABSTRACT

The present disclosure provides a method for testing an integrated circuit having a load impedance. The method includes generating a first test signal having a first frequency and a second test signal having a second frequency, wherein the second frequency is greater than the first frequency, transmitting the first test signal to a substrate having a board circuit operable to process the first signal, transmitting the second test signal to a substrate, wherein the substrate includes an impedance matching circuit operable to transform the load impedance of the integrated circuit into a desired impedance for the second frequency, and sending the first and second test signals to the integrated circuit via the substrate.

PRIORITY DATA

This application claims priority to Provisional Application Ser. No.61/118,094, filed on Nov. 26, 2008, entitled “TEST PROBE CARD,” theentire disclosure of which is incorporated herein by reference.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs and, forthese advances to be realized, similar developments in IC processing andmanufacturing are needed. In the course of integrated circuit evolution,functional density (i.e., the number of interconnected devices per chiparea) has generally increased while geometry size (i.e., the smallestcomponent (or line) that can be created using a fabrication process) hasdecreased. This scaling down process generally provides benefits byincreasing production efficiency and lowering associated costs. Suchscaling-down also produces a relatively high power dissipation value,which may be addressed by using low power dissipation devices such ascomplementary metal-oxide-semiconductor (CMOS) devices. These devicesmay then be packaged and sold as IC chips.

As technologies continue to advance, often times IC chips are used in ahigh frequency environment, such as a radio frequency (RF) environment.In addition, as the semiconductor devices get smaller and thefunctionalities of the chips continue to increase, an IC chip may have asmall area and yet have many input and output (I/O) pins operable tocontrol and program the IC chip. Consequently, the pitch size—or thedistance between the pins—becomes smaller as well. Current technologiesmay not meet the simultaneous demands of establishing proper electricalconnections to all the pins of an IC chip having a small pitch size andtesting the IC chip's high frequency response characteristics.Accordingly, a method and device to efficiently and effectively test thehigh frequency response characteristics of an IC chip having a smallpitch size is needed.

SUMMARY

One of the broader forms of an embodiment of the present inventioninvolves a method for testing an integrated circuit having a loadimpedance. The method includes generating a first test signal having afirst frequency and a second test signal having a second frequency,wherein the second frequency is greater than the first frequency;providing the first test signal to a first substrate, the firstsubstrate having a circuit operable to process the first test signal;providing the second test signal to a second substrate having animpedance matching circuit, the impedance matching circuit beingoperable to transform the load impedance into a desired impedance forthe second frequency; and sending the first and second test signals tothe integrated circuit via the second substrate.

Another one of the broader forms of an embodiment of the presentinvention involves an apparatus for testing an integrated circuit havinga load impedance and a plurality of pins separated by a first pitch. Theapparatus includes a first substrate operable to process a first testsignal having a first frequency; a second substrate coupled to the firstsubstrate, the second substrate being operable to process a second testsignal having a second frequency, wherein the first frequency does notexceed the second frequency; and an impedance matching circuit locatedon the second substrate, wherein the impedance matching circuit isoperable to transform the load impedance into a desired impedance forthe second frequency.

Yet another one of the broader forms of an embodiment of the presentinvention involves a system for testing an integrated circuit having aload impedance and a plurality of pins separated by a first pitch. Thesystem includes a tester having a source impedance and operable togenerate a first test signal having a first frequency and a second testsignal having a second frequency for testing the integrated circuit,wherein the second frequency is greater than the first frequency; afirst substrate coupled to the tester and operable to process the firsttest signal; a second substrate coupled to the first substrate andoperable to process the second test signal, wherein the second substrateincludes an impedance matching circuit operable to transform the loadimpedance into a desired impedance for the second frequency; and a probehead having a plurality of probe sensors operable to transmit andreceive the first and second test signals, wherein the probe sensorscouple the second substrate to the integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a flowchart illustrating a method for testing an IC chipaccording to various aspects of the present disclosure;

FIGS. 2-3 are diagrammatic views of a system for testing an IC chipaccording to various aspects of the present disclosure; and

FIGS. 4A-4D are exemplary embodiments of an high frequency circuit usedfor testing the IC chip.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the formation of a first feature over or on a second feature in thedescription that follows may include embodiments in which the first andsecond features are formed in direct contact, and may also includeembodiments in which additional features may be formed interposing thefirst and second features, such that the first and second features maynot be in direct contact. Various features may be arbitrarily drawn indifferent scales for simplicity and clarity.

Illustrate in FIG. 1 is a flowchart of a method 100 for testing an ICchip according to various aspects of the present disclosure. FIGS. 2-3illustrate diagrammatic views of one embodiment of a system for testingthe IC chip at various stages according to the method 100 of FIG. 1.FIGS. 4A-4D illustrate exemplary embodiments of an high frequencycircuit used for testing the IC chip. It should be noted that otherapparatuses may be implemented in the test system but are notillustrated for the sake of clarity. It is also understood thatadditional processes may be provided before, during, and after themethod 100 of FIG. 1, and that some other processes may only be brieflydescribed herein.

Referring to FIG. 1, the method 100 begins with block 110 in which afirst test signal having a first frequency and a second test signalhaving a second frequency may be generated, wherein the second frequencyis greater than the first frequency. Referring to FIG. 2, a tester 210may be used to generate test signals for testing an integrated circuit290 having a load impedance 295. The tester 210 may also be used toreceive signals from the integrated circuit 260 in response to beingtested. The tester 210 may be an automatic test equipment (ATE). Thetester 210 may include a plurality of high speed and high precisiontesting circuits 220. The tester 210 may also include a plurality ofsoftware test programs 230. The software test programs 230 may beselected or modified by an user 240 through a computer interface 250 orother suitable interface. Thus, the tester 210 has flexibility and iscapable of testing a number of different IC chips by selecting theappropriate software test program 230.

In the present embodiment, the tester 210 generates a test signal 260having a frequency 265 and another test signal 270 having a frequency275, where the frequency 265 does not exceed the frequency 275. The testsignal 260 may be used to test performance or electrical characteristicsof the integrated circuit 290 other than high frequency responsecharacteristics. For example, the test signal 260 may be used to test abaseband digital processing or power control characteristics of theintegrated circuit 290. In the present embodiment, the frequency 265associated with the test signal 260 usually does not exceed a fewhundred mega-hertz (MHz). The test signal 270 may be used to test thehigh frequency response characteristics of the integrated circuit 290,typically in an ultra-high frequency (UHF) range or a super-highfrequency (SHF) range. For example, the UHF range may span from 300 MHzto 3 GHz. The SHF range may span from 3 GHz to 30 GHz. In the presentembodiment, the frequency 275 associated with the test signal 270 isgreater than 800 MHz and may be as high as 3-5 GHz.

The method 100 continues with block 120 in which the first test signalis transmitted to a substrate having a board circuit operable to processthe first test signal. Referring now to FIG. 3, a substrate 310 may becoupled to the tester 210. The substrate 310 may be a printed circuitboard (PCB) having a plurality of conducting layers 312, 314, 316separated by a plurality of insulating layers 318, 319. The conductinglayers 312, 314, 316 and the insulating layers 318 and 319 may beplanar. The conducting layers 312, 314, 316 may include copper foil. Theinsulating layers 318, 319 may include a dielectric material. Thesubstrate 310 may also include a plurality of vias or contacts 322, 324interconnecting the conductive layers 312, 314, 316. In the presentembodiment, the substrate 310 includes a thickness 360 of about 6.35 mm.The substrate 310 is usually supplied by a vendor.

The test signal 260 may be transmitted to the substrate 310 through acoupling mechanism 315. This coupling mechanism 315 may include aconnector and a cable. The connector may include an SNA connector, anSNB connector, an SMA connector, or other suitable connectors. The cablemay include a coaxial cable or other suitable wiring. The connectors andcable may be used to route signals to and from the tester 210 andsubstrate 310. The substrate 310 may include a circuit 320. The circuit320 may be used to test the integrated circuit's 290performance/electrical characteristics other than the high frequencyresponse characteristics. For example, the circuit 320 may include adigital processing circuit. In some other embodiments, the circuit 320may also include a power control circuit. The circuit 320 may includeICs or discrete circuit components including capacitors, inductors, orresistors. In the present embodiment, the test signal 260 may be routedto the circuit 320 and processed by the circuit 320. The circuit 320 maybe electrically coupled to a plurality of pads 330 located on thesubstrate 310 by way of the vias 322 and/or 324. The pads 330 mayinclude any suitable contact pad as known in the art. The pads 330 areseparated by a pitch 340. In the present embodiment, the pitch 340includes a size of about 300 um. Also, in the present embodiment, thetest signal 260 may be routed to the pads 330 after being processed bythe circuit 320. It should be noted that the specified pitch above is amere example and that other pitch sizes may be used depending on aparticular vendor and limitations of the PCB.

The method 100 continues with block 130 in which the second test signalis transmitted to a substrate, wherein the substrate includes an highfrequency circuit operable to transform the load impedance of theintegrated circuit into a desired impedance for the second frequency.Referring to FIG. 3, a substrate 410 may be coupled to the substrate310. The substrate 410 is typically supplied by a vendor separate fromthe vendor that supplies the substrate 310. The substrate 410 mayinclude a ceramic material. Alternatively, the substrate 410 may includean organic material. In the present embodiment, the substrate 410includes a thickness 460 of about 1.53 mm. The substrate also includes aplurality of upper surface pads 425 separated by a pitch 440, whereinthe upper surface pads 425 are located on an upper surface 412 of thesubstrate 410. The upper surface 412 may be referred to as aball-grid-array (BGA) side. In the present embodiment, the pitch 440 isapproximately equal in size to the pitch 340 separating the pads 330 ofthe substrate 310. One or more of the upper surface pads 425 of thesubstrate 410 may be coupled to one or more of the pads 330 of thesubstrate 310, so that electrical signals may be transmitted andreceived between the substrate 410 and the substrate 310. This couplingmay be done by soldering the upper surface pads 425 of the substratewith the pads 330 of the substrate 310. Accordingly, the solder may actas an interface between the substrate 310 and the substrate 410. Notethat if the test signal 270 were to pass through the solder interfacefrom the substrate 310 to the substrate 410 or vice versa, the testsignal 270 may suffer signal degradation. The signal degradation may becaused by impedance mismatches.

The substrate 410 may also include a plurality of lower surface pads 430separated by a pitch 445, wherein the lower surface pads are located alower surface 413 of the substrate 410. The lower surface 413 may bereferred to as a C4 side. In the present embodiment, the pitch 445includes a size of about 130 um. The test signal 270 may be transmittedto the substrate 410 either directly from the tester 210 or through thesubstrate 310 first. In the present embodiment, the test signal 270 istransmitted to the substrate 410 through a coupling mechanism 415 andbypasses the substrate 310. This coupling mechanism 315 may include aconnector and a cable. The connector may include an SNA connector, anSNB connector, or an SMA connector. The cable may include a coaxialcable. The connector and the cable may be used to route signals to andfrom the tester 210 and substrate 410. One advantage of this embodimentis that noise and interference signals that may be present on thesubstrate 310 are not coupled to the test signal 270, since the testsignal 270 bypasses the substrate 310. Another advantage of thisembodiment is that signal degradation of the test signal 270 may bereduced since the test signal 270 does not pass through the solderinterface between the substrate 310 and the substrate 410. Consequently,a more accurate measurement of the integrated circuit's 290 highfrequency response characteristics may be obtained.

The substrate 410 also includes a high frequency circuit 450. The highfrequency circuit 410 may be separated from the main substrate 310. Thehigh frequency circuit 450 may include an impedance matching circuitthat couples a source and a load through one or more transmission lineshaving a characteristic impedance. The impedance matching circuit of thehigh frequency circuit 450 may include one or more inductors,capacitors, or resistors configured to transform an impedance of theload to a desired impedance seen by the source. In the presentembodiment, the load may be the integrated circuit 290 having the loadimpedance 295, and the source may be the tester 210 that is generatingthe test signal 270, wherein the source has a source impedance. Theimpedance matching circuit of the high frequency circuit 450 may be usedto reduce a high frequency signal reflection, or to maximize powertransfer, or to raise the signal-to-noise ratio, or to reduce the phaseand amplitude distortion, depending on the specific configuration of thehigh frequency circuit 450. For example, the load impedance 295 may beapproximately matched to the characteristic impedance of thetransmission line to reduce signal reflection. Alternatively, the loadimpedance 295 may be approximately matched to a complex conjugate of thesource impedance to maximize power transfer. Without the impedancematching circuit of the high frequency circuit 450, it may be difficultto test the high frequency response characteristics of the integratedcircuit 290, and the test results may become unreliable and invalid.Refer to FIGS. 4A-4D for various embodiments of the impedance matchingcircuit of the high frequency circuit 450.

The high frequency circuit 450 may also include other high frequencyprocessing circuits operable to function in the UHF or SHF frequencyranges. For example, the high frequency circuit 450 may includeoscillators for providing a high frequency signal, radio-frequency (RF)signal switches for routing high frequency signals, RF attenuators forattenuating high frequency signals, RF amplifiers for amplifying highfrequency signals, mixers for mixing a plurality of signals to generatea signal with a new frequency, and filters to filter out signals in anundesired frequency range. The test signal 270 may pass through and beprocessed by these other circuits in the high frequency circuit 450 aswell.

The method 100 continues with block 140 in which the first test signalis routed through the substrate to a probe head. Referring to FIG. 3, aprobe head 510 may be coupled to the substrate 410. The probe head 510may include a plurality of probe sensors 520 separated by a pitch 530.In the present embodiment, the pitch 530 is approximately equal in sizeto the pitch 445 separating the lower surface pads 430 of the substrate410, wherein the pitch 530 is about 130 um. Also, in the presentembodiment, the test signal 260 is routed from the pads 340 of thesubstrate 310 to the upper surface pads 425 of the substrate 410. Thenthe test signal 260 is routed from the upper surface pads 425 to thelower surface pads 430 of the substrate 410. Thereafter, the test signal260 is routed to the probe sensors 520 of the probe head 510.

The method 100 continues with block 150 in which the second test signalis routed to the probe head. Referring to FIG. 3, the test signal 270 isrouted through the high frequency circuit 450. The test signal 270 isthen routed to the lower surface pads 430 and then routed to the probesensors 520 of the probe head 510.

The method 100 continues with block 160 in which the first and secondtest signals are sent to the integrated circuit. Referring now to FIG.3, the integrated circuit 290 may include a plurality of pins 297,wherein adjacent pins 297 are separated by a pitch 299. In the presentembodiment, the pitch 299 is approximately equal in size to the pitch530 that separates the probe sensors 520. The probe sensors 520 areelectrically coupled to the pins 297, and the test signals 260 and 270are then sent to the integrated circuit 290 via the probe sensors 520and the pins 297. The signals 260 and 270 may then be processed by theintegrated circuit 290.

It is understood that the method 100 may continue with additional stepsto complete the testing of the integrated circuit 290. For example,after the test signals 260 and 270 are processed by the integratedcircuit 290, the integrated circuit 290 may generate one or moreresponse signals 720. The signal 720 may be received by the probe head510 through the probe sensors 520. The test signal 720 may then berouted back to the tester 210 through the substrate 410 and thesubstrate 310 and may pass through and be processed by the highfrequency circuit 450. Based on the response signals 720 and the testsignals 260 and 270, the tester 210 may complete a measurement of one ormore performance characteristics of the integrated circuit 290.

The present embodiment offers several advantages over prior art devices.One advantage of the present embodiment is that it allows having a smallpitch size for a probe head, which allows testing of ICs that have manypins (e.g., more than 1500 pins) separated by a small pitch (e.g., 130um). Another advantage of the present embodiment is that it is capableof testing devices that operate in a high frequency range, for example,a frequency range as high as 3-5 GHz. Yet another advantage of thepresent embodiment is that the lead time is shorter, typically 5-7 weekscompared to a lead time of 8-10 weeks for prior art devices. One moreadvantage of the present embodiment is that it is easy to implement. Yetanother advantage of the present embodiment is that it may have a lowermanufacturing cost.

In summary, the methods and devices disclosed provide an effective andefficient approach to test an integrated circuit. The method disclosedherein takes advantage of placing an high frequency circuit including animpedance matching circuit on a substrate. Further, the devices andapparatuses disclosed herein are inexpensive and easy to implement. Itis understood that different embodiments disclosed herein offerdifferent advantages, and that no particular advantage is necessarilyrequired for all embodiments.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A method for testing an integrated circuit having a load impedance,comprising: generating a first test signal having a first frequency anda second test signal having a second frequency, wherein the secondfrequency is greater than the first frequency; providing the first testsignal to a first substrate, the first substrate having a circuitoperable to process the first test signal; providing the second testsignal to a second substrate having an impedance matching circuit, theimpedance matching circuit being operable to transform the loadimpedance into a desired impedance for the second frequency; and sendingthe first and second test signals to the integrated circuit via thesecond substrate.
 2. The method of claim 1, wherein the sending of thefirst and second test signals includes routing the first test signalthrough the second substrate and to a probe head, and routing the secondtest signal to the probe head, the probe head being electrically coupledto the integrated circuit.
 3. The method of claim 2, further including:processing the first and second test signals with the integratedcircuit; generating a response signal with the integrated circuit;routing the response signal to a tester through the second substrate andthe first substrate, wherein the tester is operable to generate thefirst and second test signals and receive the response signal; andmeasuring a characteristic of the integrated circuit based on the firstand second test signals and the response signal.
 4. The method of claim3, wherein the providing of the second test signal to the secondsubstrate includes bypassing the second test signal from the firstsubstrate and routing the second test signal through the impedancematching circuit.
 5. The method of claim 4, further including matchingthe load impedance of the integrated circuit approximately to acharacteristic impedance of a transmission line, wherein thetransmission line couples the impedance matching circuit to theintegrated circuit and the tester.
 6. The method of claim 4, furtherincluding matching the load impedance of the integrated circuitapproximately to a complex conjugate of a source impedance of thetester.
 7. An apparatus for testing an integrated circuit having a loadimpedance and a plurality of pins separated by a first pitch,comprising: a first substrate operable to process a first test signalhaving a first frequency; a second substrate coupled to the firstsubstrate, the second substrate being operable to process a second testsignal having a second frequency, wherein the first frequency does notexceed the second frequency; and an impedance matching circuit locatedon the second substrate, wherein the impedance matching circuit isoperable to transform the load impedance into a desired impedance forthe second frequency.
 8. The apparatus of claim 7, wherein the firstsubstrate includes a plurality of pads separated by a second pitch, thesecond pitch being greater than the first pitch.
 9. The apparatus ofclaim 8, wherein the second substrate includes a plurality of uppersurface pads and a plurality of lower surface pads, wherein one or moreof the upper surface pads are electrically coupled to one or more of thelower surface pads.
 10. The apparatus of claim 9, wherein the uppersurface pads are separated by a pitch substantially the same as a sizeof the second pitch.
 11. The apparatus of claim 10, wherein the lowersurface pads are separated by a pitch substantially the same as a sizeof the first pitch.
 12. The apparatus of claim 10, wherein the uppersurface pads are located on a BGA side of the second substrate, andwherein the lower surface pads are located on a C4 side of the secondsubstrate.
 13. The apparatus of claim 12, further including a highfrequency processing circuit located on the second substrate, whereinthe high frequency processing circuit is operable to function in an RFrange and is operable to process the second test signal.
 14. Theapparatus of claim 12, wherein the high frequency processing circuitincludes an oscillator, a mixer, a filter, a low-noise-amplifier, an RFswitch, an RF attenuator, an RF amplifier, or a combination thereof. 15.The apparatus of claim 14, wherein the high frequency processing circuitand the impedance matching circuit are located on the C4 side of thesecond substrate.
 16. The apparatus of claim 15, further including acoupling mechanism located on the BGA side of the second substrate,wherein the coupling mechanism is operable to couple the secondsubstrate to a tester.
 17. A system for testing an integrated circuithaving a load impedance and a plurality of pins separated by a firstpitch, comprising: a tester having a source impedance and operable togenerate a first test signal having a first frequency and a second testsignal having a second frequency for testing the integrated circuit,wherein the second frequency is greater than the first frequency; afirst substrate coupled to the tester and operable to process the firsttest signal; a second substrate coupled to the first substrate andoperable to process the second test signal, wherein the second substrateincludes an impedance matching circuit operable to transform the loadimpedance into a desired impedance for the second frequency; and a probehead having a plurality of probe sensors operable to transmit andreceive the first and second test signals, wherein the probe sensorscouple the second substrate to the integrated circuit.
 18. The system ofclaim 17, wherein the second frequency includes frequencies from an UHFrange and an SHF range.
 19. The system of claim 18, wherein the secondsubstrate includes a coupling mechanism operable to route the secondtest signal, wherein the second test signal bypasses the first substratebefore being routed by the coupling mechanism.
 20. The system of claim19, wherein the second substrate includes a plurality of lower surfacepads that are separated by the first pitch and a plurality of uppersurface pads that are separated by a second pitch greater than the firstpitch; and wherein the first substrate includes a plurality of pads thatare separated by the second pitch for electrically coupling to theplurality of upper surface pads of the second substrate.